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rev. 1.1 6/10 copyright ? 2010 by silicon laboratories si3460 si3460 ieee 802.3af pse i nterface and dc-dc c ontroller features applications description the si3460 is a single-port, ?48 v power management controller for ieee 802.3af-comp liant power sourcing equipment (pse). designed to minimize system cost and ease implementation in embedded pse endpoint (switches) or midspan (p ower injector) applications, the si3460 operates directly from a 12 or 15 v input supply and integrates a digital pwm-based dc-dc converter for generating the ?48 v pse output supply. the ieee-required powered device (pd) detection feature uses a robust 3-point algori thm to avoid false detection events. the si3460's reference design kit also provides full ieee-compliant classification and pd disconnect. intelligent protection circuitry includes input undervoltage lockout (uvlo), classification-based current limiting, and output short-circuit protection. the si3460 is designed to operate completely independently of host processor control. an led status signal is pr ovided to indicate the port status, including detect, power good, and ou tput fault event information for use within the host system. the si3460 is pin- programmable to support endpoint and midspan applic ations as well as each of the different classification power le vels specified by the ieee 802.3af standard. a comprehensive reference design kit is available (si3460- evb), including a complete schemati c and bom (bill-of-materials) for the dc-dc converte r and pse functions. ? ieee 802.3af? comp liant pse and dc-dc controller ? autonomous operation requires no host processor interface ? complete reference design available, including si3460 controller, pse firmware, and schematic: ?? low-cost bom with compact pcb footprint ?? operates directly from a +12 or +15 v isolated supply ?? dc-dc controller generates ?48 v pse output for selv compatibility with telephony interfaces ?? supports up to 15.4 w maximum output power (class 0) ?? robust 3-point detection algorithm eliminates false detection events ?? ieee-compliant classification ?? ieee-compliant disconnect ?? inrush current control ?? short-circuit output fault protection ?? led status signal (detect, power good, output fault) ? unh interoperability test lab test report available ? extended operating range (?40 to +85 c) ? 11-pin quad flat no-lead (qfn) ?? tiny 3 x 3 mm pcb footprint; pb-free, rohs-compliant ? ieee 802.3af endpoints and midspans ? environment a and b pses ? embedded pses ? set-top boxes ? ftth media converters ? cable modem and dsl gateways pin assignments 11-pin qfn (3x3 mm) top view?pads on bottom of package isense status vsense rst deta 1 2 3 4 5 10 9 8 7 6 ctrl1 gate ctrl2 vdd 250khz gnd si3460 11 11 11 11
si3460 2 rev. 1.1 block diagram deta rst status ctrl1 ctrl2 state machine control pwm dc/dc controller: uvlo, current limiting, short circuit protection otp memory pse controller: detection classification disconnect 250khz gate isense vsense config. & led i/f osc.
si3460 rev. 1.1 3 t able of c ontents section page 1. si3460-evb applicat ion diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1. si3460-evb perform ance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 2. si3460 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3. si3460-evb performance char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.1. pse timing charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2. dc-dc converter perfor mance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4. si3460-evb functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.2. operating mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.3. operating mode sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5. design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1. isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2. external component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3. input dc supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.4. status and reset interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6. si3460 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 7. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8. package outline: 11-pin qfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1. solder paste mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.2. pcb landing pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.3. device marking of produc tion devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
si3460 4 rev. 1.1 1. si3460-evb application diagram figure 1. si3460-evb application diagram si3460 gnd deta v in +11v to 16v v out -48 v pse output (to port magnetics) rst vdd pwm bom detect bom isense v ee status 250khz ctrl1 gate vsense detect fault pgood ctrl2 note: refer to the si3460- evb user guide for complete schematic details
si3460 rev. 1.1 5 1.1. si3460-evb perf ormance characteristics when implemented according to the recommended external components and layout guidelines for the si3460- evb, the si3460 enables the following performanc e specifications in single-port pse applications. please refer to the si3460-evb user?s guide and schematics for details. table 1. selected electrical specifications (si3460-evb) parameter symbol test condition min typ max unit power supplies v in input supply range v in ?40 to +85 c ambient range 11 12, 15 16 v v in input uvlo voltage uvlo uvlo turn-off voltage at v in 10 ? ? v vdd supply voltage range v dd si3460 supply voltage range 2.7 3.3 3.6 v vdd uvlo voltage v ddmin si3460 uvlo turn-off voltage 2.7 ? ? v output supply voltage v out pse output voltage at v in = 11 v (min) to 16 v (max) ?54 ?50 ?46 v supply current i in current into v dd (including gate drive and detect) ?5?ma detection specifications minimum signature resistance r detmin 15 17 19 k ? maximum signature resistance r detmax 26.5 29 33 k ? classification specifications classification voltage v class 0ma < i class < 45 ma ?20.5 ? ?15.5 v classification current limit i class measured with 200 ? across v out 55 ? 95 ma classification current region i class _ region class 0 0 ? 5 ma class 1 8 ? 13 ma class 2 16 ? 21 ma class 3 25 ? 31 ma class 4 35 ? 45 ma protection and current control overload current threshold i cut class 0/3/4 15,400/ v out 340 400 ma class 1 5000/ v out 88 98 ma class 2 7000/ v out 154 180 ma overload current limit i lim all class levels; output = 100 ? across v out 400 425 450 ma overload time t lim output = 100 ? across v out 50 60 75 ms output power at overload p lim 15.4 17 ? w disconnect current i min disconnect current 5 7.5 10 ma efficiency system efficiency ? (p in @ v in ) to (p out @ v out )?75?%
si3460 6 rev. 1.1 2. si3460 electri cal specifications the following specifications apply to the si3460 controller. refer to tables 1, 5, 6, and 7, the si3460-evb user?s guide, and schematics for additional details about the electrical specificat ions of the si3460- evb reference design. table 2. recommended operating conditions* description symbol test conditions min typ max unit operating temperature range t a ?40 25 +85 c thermal impedance ? ja no airflow ? 75 ? c/w vdd input supply voltage vdd during all operating modes (detect, classification, disconnect) 2.7 3.3 3.6 v *note: vdd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified. table 3. absolute maximum ratings* parameter conditions max rating unit ambient temperature under bias ?55 to +125 c storage temperature ?65 to +150 c voltage on rst or any i/o pin with respect to gnd vdd > 2.2 v ?0.3 to 5.8 v voltage on vdd with respect to gnd ?0.3 to 4.2 v maximum total current through vdd and gnd 500 ma maximum output current into gate, ctrl1, ctrl2, 250khz, status, isense, rst , vsense, deta (any i/o pin) 100 ma esd tolerance human body model ?2 kv to +2 kv v lead temperature soldering, 10 seconds maximum 260 c *note: stresses above those listed in this table may cause permanent device damage. this is a stress rating only, and functional operation of the devices at thes e or any conditions above those indicat ed in the operational listings of this specification is not implied. exposure to maximum rating cond itions for extended periods may affect device reliability.
si3460 rev. 1.1 7 table 4. electrical characteristics* description symbol test conditions min typ max unit digital pins: gate, ctrl1, ctrl2, 250khz, status (output mode), rst output high voltage v oh i oh =?3ma i oh =?10a i oh = ?10 ma 0.8 x vdd vdd ? 0.1 ? ? ? 0.7 x vdd ? ? ? v output low voltage v ol i ol =8.5ma i ol =10a i ol =25ma ? ? ? ? ? 0.4 x vdd 0.6 0.1 ? v input high voltage v ih any digital pin 0.7 x vdd v input low voltage v il any digital pin ? ? 0.3 x vdd v input leakage current i il v in =0v ? 1 ? a analog pins: isense, vsense, deta, status (input mode) input capacitance ?5?pf input leakage current i il ?1?a *note: vdd = 2.7 to 3.6 v, ?40 to +85 c unless otherwise specified.
si3460 8 rev. 1.1 3. si3460-evb performance characteristics when implemented in accordance with the recommended ex ternal components and layout guidelines, the si3460 controller enables the followi ng typical performance characteristics in single-port pse applicat ions. refer to the si3460-evb applications note, schematics, and user's guide for more details. table 5. pse performance characteristics 1 parameter symbol conditions min typ max unit protection and current control overload current limit i lim output = 100 ? across v out 400 425 450 ma overload current threshold 3 i cut class 0/3/4 15,400/ v out 340 400 ma class 1 5000/ v out 88 98 ma class 2 7000/ v out 154 180 ma overload current limit i lim all class levels; output = 100 ? across v out 400 425 450 ma overload time t lim output = 100 ? across v out 50 60 75 ms output power at overload p lim 15.4 17 ? w disconnect current i min disconnect current 5 7.5 10 ma detection specifications 2 detection voltage v det detection point 1 (w/ 10 k ? source) detection point 2 (w/ 10 k ? source) detection point 3 (w/ 10 k ? source) ? ? ? 4.5 7.5 4.5 ? ? ? v minimum signature resistance r detmin 15 17 19 k ? maximum signature resistance r detmax 26.5 29 33 k ? classification specifications 2 classification voltage v class 0 ma < iclass < 45 ma ?20.5 ? ?15.5 v classification current limit i class measured with 200 ? across v out 55 ? 95 ma classification current region i class_region class 0 class 1 class 2 class 3 class 4 0 8 16 25 35 ? ? ? ? ? 5 13 21 31 45 ma ma ma ma ma notes: 1. typical specifications are based on an am bient operating temperature of 25 oc and v in = +12 v unless otherwise specified. 2. see ?3. si3460-evb performance characteristics? for more details. 3. absolute classification current limits are configurable.see section "4.3.2. classification" on page 12.
si3460 rev. 1.1 9 3.1. pse timing characteristics when implemented in accordance with the recommended ex ternal components and layout guidelines, the si3460 controller enables the followi ng typical performance characteristics in single-port pse applicat ions. refer to the si3460-evb applications note, schematics, and user's guide for more details. 3.1.1. pse timing diagrams the basic sequence of applying power is shown in figure 2. following is the description of the function that must be performed in each phase. figure 2. detection, classification, powerup, and disconnect sequence table 6. pse timing* description symbol test conditions min typ max unit endpoint detection delay cycle t det_cycle time from pd connection to port to completion of detection process. 70 ? 400 ms detection time t detect time required to measure pd signature resistance. ?70? ms classification delay cycle t class_cycle time from successful detect mode to classification complete. 10 ? 50 ms classification time t class 10 ? 50 ms power-up turn-on delay t pwrup time from when a valid detection is completed until v out power is applied ?30? ms midspan detect backoff time t bom 2?? s current limit time t lim ?60? ms disconnect delay t dc_dis ?350? ms *note: these typical specifications are based on an ambient operating temperature of 25 oc and v in =+12v. voltage t det_cycle time (msec) 2.8 v 10 v 15.5 v 44 v 57 v 20.5 v t class_cycle t pwrup
si3460 10 rev. 1.1 3.2. dc-dc converter pe rformance characteristics the dc-dc converter utilizes a digital control loop architecture operating at 250 khz. th e complete converter is comprised of the si3460 controller and the external co mponents in the si3460-evb schematics. the performance specifications in table 7 are typical for the si3460-evb reference design. table 7. dc-dc performance 1 parameter symbol conditions min typ max unit dc-dc controller perfo rmance characteristics 2 pwm operating frequency f pwm ? 250 ? khz efficiency ? v in to v out ?75? % load regulation r load minimum to maximum load ? 1 ? % line regulation r line for v in ranging from 11 to 16 v ? 1 ? % output ripple r 250 khz pwm frequency < 500 hz ? ? 100 200 ? ? mv notes: 1. typical specifications are based on an ambient operating temperature of 25 oc and v in =+12v. 2. see ?3. si3460-evb performance characteristics? for more details.
si3460 rev. 1.1 11 4. si3460-evb functional description in combination with low-cost exter nal components, the si3460 controller provides a co mplete pse solution for embedded poe applications. included in the si3460-evb re ference design is a digital pwm controller-based dc-dc converter that simplifies overall system design by generat ing the ?48 v pse supply voltage. an isolated 11 to 16 v input dc supply is all that is needed to supply the si3460-evb reference design. refer to the si3460-evb user?s guide and schematics for descriptions in the following sections. 4.1. reset state at powerup or if reset is held low, the si3460 is in an inactive state with the pwm turned off (the switcher fet, m1, is off) and the pass fet, m2, is off. 4.2. operating mode configuration at powerup, the si3460 reads the voltage on the status pin, which is set by a resistor divider from v ee to chip ground. the status pin voltage level configures all of the si3460's operating modes as summarized in table 8. after powerup, the status pin drives the base of a pnp tr ansistor that controls an le d. to maintain an accurate voltage level at the transistor base, it is recommended that the parallel resistance setting the pin voltage be less than 1 k ? . table 8. operating modes status pin voltage operating mode power level supported (w) classes supported midspan/ endpoint restart action on fault or overload event condition pin voltage at v ee (no resistors populated) 15.4 all class levels endpoint auto restart after 2 s 3.0 v 7.0 class 1 or 2 endpoint auto restart after 2 s 2.75 v 4.0 class 1 endpoint auto restart after 2 s 2.5 v 15.4 all class levels endpoint restart on rst 2.25 v 7.0 class 1 or 2 endpoint restart on rst 2.0 v 4.0 class 1 endpoint restart on rst 1.75 v 4.0 class 1 midspan restart on rst 1.5 v 7.0 class 1 or 2 midspan restart on rst 1.25 v 15.4 all class levels midspan restart on rst 1.0 v 4.0 class 1 midspan auto restart after 2 s 0.5 v 7.0 class 1 or 2 midspan auto restart after 2 s < 0.25 v (pullup resistor only) 15.4 all class levels midspan auto restart after 2 s
si3460 12 rev. 1.1 4.3. operating mode sequencing 4.3.1. detection after powerup and passing the uvlo threshold voltage of 10 v, the si3460 enters into the detection state, with fet m2 off and the dc-dc conv erter disabled so as to g enerate no out put. prior to turnin g on the pse output fet m2 and enabling the 250 khz square wave for the dc-dc converter, a valid detection sequence must take place. according to the ieee specificat ions, the detection process consists of sensing a nominal 25 k ? signature resistance in parallel with up to 0.15 f of capacitance. to eliminate the possibility of false detection events, the si3460-evb reference design pe rforms a robust 3-po int detection sequence by varying the voltage across the sense bridge r1, r2, and r3. the fourth leg of the sense bridge is the load that connects to the drain of m2 and returns to v ee via d8 and l1. at the beginning of the detection sequence, v out is at zero output voltage for 250 ms. with a 10 k ? source impedance, v out is then varied from 4.5 to 7.5 v and then back to 4.5 v for 20 ms at each level. if the pd's signature resistance is in the rgood range of 19 to 26.5 k ? , the si3460 proceeds to classification and powerup. if the pd resistance is not in this range, th e detection sequence repeats continuously. detection is sequenced approximately every 320 msec an d repeats until rgood is sensed, indicating a valid pd has been detected. the status led (d13) is flashed at the 320 ms rate in synchr onization with the detection process to indicate the pse is searching for a valid pd. 4.3.2. classification after a valid pd is detected, the pass transistor, m2, and the pwm controller are turned on and programmed for an output voltage of 18 v with a current limit of 75 ma. the current measured during the classification process determines the class level of the pd. if the class level of the pd is not within th e supported level as set by the initial voltage on the si3460's status pin (refer to the op erating mode configuration section above), an error is declared and the led blinks rapidly. this is referred to as classification-based power denial. if the class level is in the supported range, the si3460 procee ds to powerup. this is referred to as classification-b ased power granting. classification level is determin ed according to the current at isense as shown in table 9. if the classification level is at a greater power than c an be supported based on r28 and r30, an error condition is reported by flashing the led at a 10 hz rate for two se conds before the state machine goes back to the detection cycle. 4.3.3. classification-based current limiting current limits (i cut )are set based on the classification voltage on th e status pin at powerup. refer to table 9 for current limits. table 9. classification levels isense current (nominal) classification level minimum power level overload current threshold i cut (max) overload current limit i lim (max) < 6.5 ma class 0 15.4 w 400 ma 450 ma 6.5ma to 14.5 ma class 1 4 w 98 ma 450 ma 14.5 ma to 23 ma class 2 7 w 180 ma 450 ma > 23 ma class 3 or 4 15.4 w 400 ma 450 ma
si3460 rev. 1.1 13 4.3.4. dc-dc conv erter ramp-up after the optional classification seque nce, the dc-dc converter is powered up to ?50 v with a current limit corresponding to the values indicated in table 9. after powerup, power is applied to v out as long as there is not an overcurrent fault, disconnect, or input undervoltage (uvlo) condition. the status led is continuously lit when power is applied. if the output power exceeds the level determined by the initial voltage of the status pin, the si3460 will declare an erro r and shut down the port, flas hing the led rapidly to indica te the error (for either two seconds or until reset as determined by the initial voltage on the status pin). 4.3.5. dc-dc converter soft start the pwm control loop of the dc-dc converter is designed to produce a gradual rise in output voltage to eliminate any inrush current issues. the nominal set point of the dc-dc converter is ?50 v. v out at ?50 v results in 0.930 v at the vsense pin. it is possible for there to be almost no load on the dc-d c converter; so, the duty cycle is ramped slowly up to the dc set point. the duty cyc le is initially set to zero (dc-dc converter off). once the desired voltage set point is reached, the feedback path from vsense is enabled, and the converter is allo wed to regulate at the desired set point. 4.3.6. disconnect the si3460 implements a robust disconnec t algorithm. if the output current level drops below 7.5 ma (nominal) for more than 350 ms, the si3460 will declare a pd disconnect, and the dc-dc converter clock (250 khz) and fet m1 will be turned off. as set by the initial voltage on the status pin, the si3 460 will then automatically resume the detection process after 250 ms for "endpoint mode" and two seconds for "midspan mode." the difference in these two backoff timings is specified by the iee 802.3af st andard for the midspan and endpoint operating modes. 4.3.7. current limit control the si3460's overcurrent trip point is determined by the output power set during the classification stage power granting process. if the output current exceeds the threshold, a timer counts up towards a time-out of 60 ms. if the current drops below the set threshold, the timer counts down towards zero at 1/16th the rate. if the timer reaches 60 ms, an overcurrent fault is declared, and the channel is shut down by turning off th e dc-dc converter clock and then turning off the fet m1. after an overcurrent fault event, the led will flash rapidly. as set by the initial voltage on the status pin at power up, the si3460 will then automa tically resume the detection process for "automatic restart configuration" unless the si3460 is conf igured in a "restart after a reset condition" mode and a fault condition is detected; in that ca se, the led will flash rapidly, and the detection process will automatically start again afte r 2.2 seconds. power will not be provided unti l an open-circuit c ondition is detected. once the si3460-evb detects an open-circuit condition (normally by removing the ethernet cable from the si3460- evb?s rj-45 jack labelled ?to pd?) , the detection process begins, the status led blinks at the rate of 3 times per second, and the si3460 is then allowed to go into cl assification and powerup mode if a valid pd signature resistance is detected. 4.3.8. uvlo the si3460-evb reference design is optimized for 12 to 15 v nominal in put voltages (11 v min to 16 v maximum). if the input voltage drops below 10 v in detection mode or if the output voltage drops below 10 v in classification or powerup mode, a uvlo condition is declared, which gene rates the error condition (led flashing rapidly). an undervoltage event is a fault condition reported throug h the status led as a rapid blinking of 10 flashes per second. the uvlo condition is continuously monitored in all operating states. 4.3.9. status led function during the normal detection sequence, the status led flashes at approximately 3 times per second as the detection process continues. after successful power up, the led glows continuously. if there is an error condition (i.e., class level is beyond programmed value, or a fault or over current condition has been detected), the led flashes rapidly at 10 times per second). this occurs for two seconds for normal error delay and, in the case of the "restart after a reset condition", the led will flash rapidly, and the detection process will automati cally start again after 2.2 s and power will not be provided until an open circuit condition is detected. once the si3460-evb detects an open circuit condition, the led blinks at 3 times per second. if the powered device (pd) is disconnected so that a di sconnect event occurs, the led will start flashing at 3 times per second once the detect process resumes.
si3460 14 rev. 1.1 5. design considerations 5.1. isolation the si3460-evb's pse ou tput power at v out is not isolated from the input power source (v in ). isolation of pse output power requires that the input be isolated from earth ground. typically, an ac to dc power supply or "wall wart" is used to provide the 12 v power so the output of this supply is isolated from earth ground. 5.2. external component selection detailed notes on extern al component selectio n are provided in the si3460-evb user's guide schematics and bom. in general, these reco mmendations must be followed closely to ensure output power stability and ripple (power stage components), surge protection (surge protection diode), and ov erall ieee 802. 3 compliance. 5.3. input dc supply the input power supply should be rated for at least 25% higher power level than the output power level chosen. this is primarily to account for the 75 to 80% nominal efficiency perf ormance of the si3460 -evb reference design. for example, to support a class 0 pse, for example, the input supply shou ld be capable of supplying 19.25 w (15.4 w x 1.25 = 19.25 w). 5.4. status and reset interface to reference the reset and status pins to system grou nd, the level shifting method shown in figure 3 can be used. refer to the schemati c in the si3460-evb document. figure 3. status and reset pin interfa ce when referenced to system ground vdd si3460 status rst gnd +12v +8.7v status output shunt regulator r*3.3/2.7 rst control r8 (66.5 k ? ) r7 (40.2 k ? ) 806 ? system gnd 405 ? r40 (332 ? ) 1 uf/ 6.3 v r22 (1 k ? ) u1 tlv431
si3460 rev. 1.1 15 6. si3460 pin descriptions si3460 pin functionality is described in table 10. note that the information applies to the si3460 device pins, while the si3460-evb user?s guide describes the inpu ts and outputs of th e evaluation system. the electrical characterist ics of the si3460-evb are summarized in ta ble 1 on page 5. re fer to the complete si3460-evb schematics and bo m listing for inform ation about the external comp onents needed fo r the complete pse and dc-dc controlle r application circuit. table 10. si3460 pin functionality pin # pin name pin type pin function 1 gate digital output a logic low on this pin turns on the output fet to enable the pse output voltage. refer to the si34 60-evb schematics for the circuit connections between the external fet and this pin. 2 ctrl1 digital output the output of this pin is averaged with ctrl2 to control pwm duty cycle for the dc-dc controller. this ou tput also controls the dc output for the detection circuitry. 3 vdd power 3.3 v power supply input. 4 ctrl2 digital output the output of this pin is averaged with ctrl1 to control pwm duty cycle for the dc-dc controller. this ou tput also controls the dc output for the detection circuitry. 5 250khz digital output this is a 250 khz square wave (50% duty cycle) that is filtered into a triangular wave signal for the dc-dc controller. the 250 khz output on this pin is gated off when it is desired to keep the switcher fet off. 6 deta analog input deta is an analog input pin. du ring the detection process, the ctrl1 and ctrl2 pin duty cycle is varied to generate filtered dc voltages across a resistive bridge. the null indicator for this bridge is connected to pin deta. 7 vsense analog input vsense is an analog input used fo r sensing the pse output volt- age. isense status vsense rst deta 1 2 3 4 5 10 9 8 7 6 ctrl1 gate ctrl2 vdd 250khz gnd 11 11 11 11
si3460 16 rev. 1.1 8rst digital input active low reset inpu t. when low (to gnd), places the si3460 device into an inactive state. the dc-dc converter is disabled. when pulled high, the device begins th e detection process sequence. the dc-dc begins to function after a valid r good signature is detected, indicating a valid pd has been detected. 9 isense analog input isense is an analog input connected to a current sense resistor for output current sensing. 10 status analog in/digital out at powerup, the voltage on this pin is sensed to configure the clas- sification level, mid span timi ng mode, and the device?s restart behavior when a fault condition is detected. refer to "4.2. operating mode configuration" on page 11 and "4.3.9. status led function" on page 13 for more information. after reading the voltage present at this pin at powerup, the status pin becomes a digital output used to control an external led, which indicates when a detect, power good, or output fault condition has occurred. a logic low turns the led on, and logic high turns the led off. 11 gnd gnd ground connection for the si3460. this is not earth ground. refer to the si34 60-evb schematics for more info rmation. table 10. si3460 pin functionality (continued) pin # pin name pin type pin function
si3460 rev. 1.1 17 7. ordering guide ordering part number firmware revision description package information ambient temperature range si3460-e02-gm (not recommended for new designs) 0.6.7 single-port pse controller with integrated dc-dc con- verter for embedded appli- cations 11-pin, 3mm ? 3 mm qfn. rohs compliant. ?40 to 85 c si3460-e03-gm 0.6.8 si3460-evb n/a si3460 evaluation board and reference design evaluation board n/a notes: 1. add ?r? to part number to denote tape- and-reel option (e.g., SI3460-E03-GMR). 2. the ordering part number above is not the same as the dev ice mark. see"8.3. device ma rking of production devices" on page 21 for more information.
si3460 18 rev. 1.1 8. package outline: 11-pin qfn figure 4 illustrates the package details for the si3460. table 11 lists the values for the dimensions shown in the illustration. the si3460 is pa ckaged in an industry-sta ndard, 3x3 mm, rohs-compli ant, pb-free, 11-pin qfn package. figure 4. qfn-11 package drawing table 11. package diagram dimensions dimension min nom max a 0.80 0.90 1.00 a1 0.03 0.07 0.11 a3 0.25 ref b 0.18 0.25 0.30 d3 . 0 0 b s c . d2 1.30 1.35 1.40 e0 . 5 0 b s c . e3 . 0 0 b s c . e2 2.20 2.25 2.30 l .45 .55 .65 aaa ? ? 0.15 bbb ? ? 0.15 ddd ? ? 0.05 eee ? ? 0.08 notes: 1. all dimensions shown are in millim eters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outl ine mo-243, variation veed except for custom features d2, e2, and l which are toleranced per supplier designation. 4. recommended card reflow profile is per the jedec/ipc j-std-020c specification for small body components.
si3460 rev. 1.1 19 8.1. solder paste mask figure 5. solder paste mask 0.50 mm lt e e d e lb k d2 b l d4 0 . 1 0 m m 0.50 mm 0.35 mm 0.30 mm 0.10 mm 0.20 mm 0.30 mm 0.20 mm 0.60 mm 0.70 mm d4 b 0.30 mm 0.35 mm e2 0.20 mm
si3460 20 rev. 1.1 8.2. pcb landing pattern figure 6. typical qfn-11 landing diagram lt e e d e lb k b l d4 0 . 1 0 m m 0.50 mm 0.35 mm 0.30 mm 0.10 mm 0.20 mm d4 b 0.30 mm 0.20 mm e2 d2 0.10 mm
si3460 rev. 1.1 21 8.3. device marking of production devices line 1 is the part number, line 2 is the lot code, and line 3 is the date code. the part number marking is different for si3460-e02 devices an d si3460-e03. the silicon revision letter is the first letter of t he lot code ("e" for both si3460- e02 and si3460-e03 devices). figure 8 sh ows how to decode the top side marking. figure 7. qfn 11 top marking table 12. top marking explanation line 1 marking: pin 1 identifier circle = 0.25 mm diameter product id 6003 60 = si3460; 03 = firmware revision 03 line 2 marking: ettt = trace code assembly trace code e = product revision ttt = assembly trace code line 3 marking: yww = date code assigned by the assembly contractor. y = last digit of current year (ex: 2009 = 9) ww = current work week lead-free designator + 6003 ettt yww+
si3460 22 rev. 1.1 d ocument c hange l ist revision 0.4 to revision 1.0 ? added table 1 specification values on page 5. ? updated table 5 specification values for i cut limits on page 8. ? revised ?4.3.2. classification? text description on page 12. ? added i cut and i lim current limits to table 9 on page 12. ? added "4.3.3. classification-based current limiting" on page 12. ? updated ?4.3.4. dc-dc converter ramp-up? text description on page 13. ? updated ?4.3.7. current limit control? text description on page 13. ? updated "8. package outlin e: 11-pin qfn" on page 18. revision 1.0 to revision 1.1 ? updated "7. ordering guide" on page 17. ? updated "8.3. device marking of production devices" on page 21. ? updated figure 7, ?qfn 11 top marking,? on page 21.
si3460 rev. 1.1 23 n otes :
si3460 24 rev. 1.1 c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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